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FPGA Verilog Police siren sound in speaker and PWM LEDs Xilinx Spartan 3 development board
 
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Code for the video... support me by accessing my blog through an Ad and just skip the ad after 5 secs: http://rapidtory.com/C3oF DONATE with PAYPAL: [email protected] Support me through Patreon! https://www.patreon.com/JuanFelipePV DONATE with BITCOIN: 1PJJiXCLqNPuQtyRebwUHdwqNJGaZsfVGt DONATE with Ethereum: 0x4671bfa20243634234f73a6ffc5f214cf27c921b DONATE with LiteCoin: LhKtK8KEoxdpVBJLZLbEZKjjDpeHmenAPd DONATE with ZCASH: t1Md3vXgojrk5cX6jqhFpjaTWQ1fbLGFZZg
Views: 417 Juan Felipe Proaño
FPGA Video Transmission
 
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In this demonstration, we use two VEEK-MT FPGA Development Kits to showcase the transmission of video signals from one kit to the other via A/D conversion. Featuring the high-density Altera Cyclone IV FPGA, the VEEK-MT is perfect for all kinds of multimedia applications.
Views: 5633 terasicTV
FPGA VERILOG DS18B20 Temperature sensor one wire Xilinx sparatan 3 development board
 
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DONATE with PAYPAL: [email protected] Support me through Patreon! https://www.patreon.com/JuanFelipePV Code: http://quitoart.blogspot.co.uk/2017/11/fpga-verilog-ds18b20-temperature-sensor.html The DS18B20 digital thermometer provides 9-bit to 12-bit Celsius temperature measurements and has an alarm function with nonvolatile user-programmable upper and lower trigger points. The DS18B20 communicates over a 1-Wire bus that by definition requires only one data line (and ground) for communication with a central microprocessor. In addition, the DS18B20 can derive power directly from the data line (“parasite power”), eliminating the need for an external power supply. Each DS18B20 has a unique 64-bit serial code, which allows multiple DS18B20s to function on the same 1-Wire bus. Thus, it is simple to use one microprocessor to control many DS18B20s distributed over a large area. Applications that can benefit from this feature include HVAC environmental controls, temperature monitoring systems inside buildings, equipment, or machinery, and process monitoring and control systems. Suppoert me by accessing my blog through an Ad: http://adf.ly/1KcSpd DONATE with BITCOIN: 1PJJiXCLqNPuQtyRebwUHdwqNJGaZsfVGt DONATE with Ethereum: 0x4671bfa20243634234f73a6ffc5f214cf27c921b DONATE with LiteCoin: LhKtK8KEoxdpVBJLZLbEZKjjDpeHmenAPd DONATE with ZCASH: t1Md3vXgojrk5cX6jqhFpjaTWQ1fbLGFZZg
Views: 732 Juan Felipe Proaño
FPGA killed the video capture star
 
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Joel Stanley http://lca2015.linux.org.au/schedule/30209/view_talk Recording video for streaming and storage is hard. Open hardware is fun. Lets create some open hardware to record video! The timvideos project is an effort to create an easy to use, modern video recording workflow for conferences like linux.conf.au. Central to this effort is HDM2USB, a FPGA based HDMI capture board. The FPGA system captures video, does compression, USB streaming, and more, and it’s built on open hardware to boot. Come learn about the challenges of designing an open video capture system, and how to use open source to help you along the way.
Conway's Game of Life on FPGA
 
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This project was completed under Electronics CLub in the summer of 2014 at IIT-Kanpur. A Mojo FPGA board with a Spartan 6 chip is running the famous zero-player 'Game of Life', invented by John Conway. THe output is displayed on a VGA display, as well as on a LED matrix.
Artix7 FPGA Game
 
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Recreated this game: http://www.puzzlebeast.com/monkmaze/ to be played on the Nexsys 4 FPGA development board. The following MATLAB Script was used to convert the PNG files into COE for uses with Xilinx Vivado RAM blocks. function img2 = IMG2coe12(imgfile, outfile) % EGR426 - FPGA Design % Kurt VonEhr % Script handles the conversion of .PNG files to a COE file % for use with Xilinx Vivado RAM blocks. % Example: % img2 = IMG2coe12('REH45x226.bmp', 'REH8.coe'); [img ,map,alpha] = imread(imgfile); height = size(img, 1); width = size(img, 2); s = fopen(outfile,'wb'); %opens the output file fprintf(s,'%s\n','; VGA Memory Map '); fprintf(s,'%s\n','; .COE file with hex coefficients '); fprintf(s,'; Height: %d, Width: %d\n\n', height, width); fprintf(s,'%s\n','memory_initialization_radix=16;'); fprintf(s,'%s\n','memory_initialization_vector='); cnt = 0; img2 = img; alpha2 = alpha; for r=1:height for c=1:width cnt = cnt + 1; R = img(r,c,1); G = img(r,c,2); B = img(r,c,3); A = alpha(r,c); Rb = dec2bin(double(R),8); Gb = dec2bin(double(G),8); Bb = dec2bin(double(B),8); Ab = dec2bin(double(A),8); img2(r,c,1) = bin2dec([Rb(1:4) '0000']); img2(r,c,2) = bin2dec([Gb(1:4) '0000']); img2(r,c,3) = bin2dec([Bb(1:4) '0000']); alpha2(r,c) = bin2dec([Ab(1:4) '0000']); Outbyte = [ Rb(1:4) Gb(1:4) Bb(1:4) Ab(1:4)]; RDec = bin2dec(Outbyte(1:4)); GDec = bin2dec(Outbyte(5:8)); BDec = bin2dec(Outbyte(9:12)); ADec = bin2dec(Outbyte(13:16)); if (RDec ~= 0) fprintf(s,'%X',bin2dec(Outbyte)); elseif((RDec == 0) && (GDec ~= 0)) fprintf(s,'0%X',bin2dec(Outbyte)); elseif((RDec == 0) && (GDec == 0) && (BDec ~= 0)) fprintf(s,'00%X',bin2dec(Outbyte)); else fprintf(s,'000%X',bin2dec(Outbyte)); end if ((c == width) && (r == height)) fprintf(s,'%c',';'); else if (mod(cnt,32) == 0) fprintf(s,'%c\n',','); else fprintf(s,'%c',','); end end end end fclose(s);
Views: 409 Kurt VonEhr