Please watch: "Earn money at home in simple steps..." https://www.youtube.com/watch?v=LN6W15AN5Ho -~-~~-~~~-~~-~- LIKE | SHARE | SUBSCRIBE | COMMENT --------------------------------------------- THIS TUTORIAL HELPS TO UNDERSTAND 4 BIT DECADE COUNTER WITH ASYNCHRONOUS RESET -------------------------------------------- PLZ REFER THE FOLLIWING LINK FOR VHDL CODE:- https://drive.google.com/file/d/0B7-SqtQEyRRabXF4YW9HSlVkdU0/view?usp=drivesdk
Views: 5196 Viral Media Telecomm
BINARY COUNTER DESIGN , 3 BIT BINARY COUNTER BY t- FLIP FLOPS
Views: 19658 OnlineTeacher
Digital Electronics: Difference between Synchronous and Asynchronous Sequential Circuits. Contribute: http://www.nesoacademy.org/donate Website ► http://www.nesoacademy.org/ Facebook ► https://goo.gl/Nt0PmB Twitter ► https://twitter.com/nesoacademy Pinterest ► http://www.pinterest.com/nesoacademy/
Views: 264974 Neso Academy
NOTE: No Audio for around 15 minutes from 1:02:51 to 1:19:14 (I have added Subtitles at that point) Topics Covered: - Designed logic to interface Clock's Hrs and Mins with Nexys 3 FPGA's seven segments - Verilog Code of Digital Clock - Some Tips and Tricks using Notepad++ You can download clock code and ucf from here http://tinyurl.com/clock-verilog-code SUBSCRIBE! https://www.youtube.com/channel/UCRZQvLnnlkJ0vHXGwjNsfNw?sub_confirmation=1 This course was taught at Abasyn University Islamabad, Fall 2016 http://www.abasynisb.edu.pk/
Views: 5417 Renzym Education
This tutorial on Converting Binary to BCD accompanies the book Digital Design Using Digilent FPGA Boards - VHDL / Active-HDL Edition which contains over 75 examples that show you how to design digital circuits using VHDL, simulate them using the Aldec Active-HDL simulator, and synthesize the designs to a Xilinx FPGA. Visit www.lbebooks.com for more information or to purchase this inexpensive, informative, award winning book.
Views: 19298 LBEbooks
This tutorial on Multiplexing 7-Segment Displays accompanies the book Digital Design Using Digilent FPGA Boards - VHDL / Active-HDL Edition which contains over 75 examples that show you how to design digital circuits using VHDL, simulate them using the Aldec Active-HDL simulator, and synthesize the designs to a Xilinx FPGA. Visit www.lbebooks.com for more information or to purchase this inexpensive, informative, award winning book.
Views: 46325 LBEbooks
Simple 0 to f counter in seven segment display can be made using flip flops. Here FPGA cyclone iv is used to process the logic circuit. The steps of using the FPGA board and the quartus software is shown clearly. It count numbers from 0 to hexadecimal f when a push button is pressed.
Views: 49 Hishan Indrajith
To see how Gray code is generated pls watch this video https://www.youtube.com/watch?v=4nGcRilcDlM a better audio version is here, https://youtu.be/vUjKP29Tm50
Views: 7300 sacademy
Digital Electronics: Full Adder Implementation using Decoder. Logic implementation using decoder Contribute: http://www.nesoacademy.org/donate Website ► http://www.nesoacademy.org/ Facebook ► https://goo.gl/Nt0PmB Twitter ► https://twitter.com/nesoacademy Pinterest ► http://www.pinterest.com/nesoacademy/
Views: 248102 Neso Academy
In this video, we show the design and the Verilog codes for a 4-bit twos-complement circuit. We demonistrate the correctness of the design using the modelsim simulator and the Altera Qurtus prime IDE.
Views: 1041 Abdullah Balamash
In this Verilog tutorial, we demonstrate usage of Verilog $display system task for debugging. Complete example from the Verilog tutorial: http://www.edaplayground.com/s/example/352 Recommend viewing in 720p quality or higher. About EDA Playground: EDA Playground is a web browser-based integrated development environment (IDE) for simulation of SystemVerilog, Verilog, VHDL, and other HDLs. EDA Playground is a free web application that allows users to edit, simulate, share, synthesize, and view waves for hardware description language (HDL) code. It is the first online HDL development environment and waveform viewer for the semiconductor industry. EDA Playground homepage: http://www.edaplayground.com Engineers have used EDA Playground for: -- creating hands-on training for students -- demonstrating best practices to other engineers -- asking SystemVerilog questions on StackOverflow and other online forums -- testing candidates' coding skills during technical interviews (phone and in-person) -- quick prototyping -- trying something before inserting the code into a large code base -- checking whether their RTL syntax/code is synthesizable EDA Playground is actively seeking partners to integrate additional EDA tools. Future tools will include formal verification, linting, and analog and mixed-signal support.
Views: 12613 EDA Playground
In this video lecture we will learn about parity bit, checker and it's circuit. Follow :) Youtube: https://www.youtube.com/c/BikkiMahato Facebook: https://www.facebook.com/mahatobikki Facebook Page:https://www.facebook.com/youtubebikki Twitter:https://twitter.com/mahato_bikki Instagram:https://www.instagram.com/bikkimahato Google+:https://plus.google.com/u/0/+BikkiMahato Blogger:https://bikkimahato.blogspot.in Support :) Paytm : 8100147475 PhonePe : 8100147475 Patreon : https://www.patreon.com/bikkimahato Instamojo : https://www.instamojo.com/@bikkimahato Paypal : https://www.paypal.me/bikkimahato
Views: 89065 Bikki Mahato
Digital Electronics: ASM Chart ASM Chart for Moore State Machine: https://youtu.be/kNG0l2vAGjw Contribute: http://www.nesoacademy.org/donate Website ► http://www.nesoacademy.org/ Facebook ► https://goo.gl/Nt0PmB Twitter ► https://twitter.com/nesoacademy Pinterest ► http://www.pinterest.com/nesoacademy/
Views: 145711 Neso Academy
The Quartus II Pin Planner helps you visualize, plan, and assign device I/O pins in a graphical view of the target device package. You can quickly locate various I/O pins and assign them design elements or other properties to ensure compatibility with your PCB layout. The Pin Planner can also help with early pin planning by allowing you to plan for and assign nodes not yet defined in the design. Follow Intel FPGA to see how we’re programmed for success and can help you tackle your FPGA problems with comprehensive solutions. Facebook: https://www.facebook.com/IntelFPGA Twitter: https://twitter.com/intelfpga LinkedIn: https://www.linkedin.com/company/intelfpga For technical questions, contact the Intel Community: https://forums.intel.com/s/?language=en_US
Views: 6843 Intel FPGA
For this project I was asked to implement a simple digital clock with an "alarm" feature. The clock's time and desired alarm time is programmed by the user. The display is output on four 7-Segment Displays whose output is based on toggle switches located on the board. The clock enters preset mode when a toggle switch for hour only, minute only, second only is set to a logic value of 1 - here the display reads only the desired unit of time. Once out of preset mode the display outputs depending on a toggle switch: hh:mm or mm:ss. An LED is used to denote am/pm for the clock and the alarm. Once the alarm's hour, minute, and am/pm matches the current time's hour, minute, and am/pm, LEDs on the board would blink indicating the alarm (this because the Spartan 3 Board does not possess any audio outputs).
Views: 611 Dan Ehlers